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4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO)
Advanced Information 4 194 304 words by 4-bit organization 0 to 70 C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20
HYB5116405BJ/BT -50/-60/-70 HYB5117405BJ/BT -50/-60/-70
* * *
-60 60 15 30 104 25
-70 70 20 35 124 30 ns ns ns ns ns
* *
* * * * * * *
Single + 5 V ( 10 %) supply Low power dissipation max. 550 mW active (HYB5116405BJ/BT-50) max. 495 mW active (HYB5116405BJ/BT-60) max. 440 mW active (HYB5116405BJ/BT-70) max. 660 mW active (HYB5117405BJ/BT-50) max. 605 mW active (HYB5117405BJ/BT-60) max. 550 mW active (HYB5117405BJ/BT-70) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Hyper page mode (EDO) capability All inputs, outputs and clocks fully TTL-compatible 4096 refresh cycles / 64 ms for HYB5116405BJ/BT (4k-Refresh) 2048 refresh cycles / 32 ms for HYB5117405BJ/BT (2k-Refresh) Plastic Package: P-SOJ-26/24 300 mil P TSOPII-26/24 300 mil
Semiconductor Group
1
1.96
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
The HYB 5116(7)405BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 5116(7)405BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116(7)405BJ/BT to be packaged in a standard SOJ 26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5116405BJ-50 HYB 5116405BJ-60 HYB 5116405BJ-70 HYB 5116405BT-50 HYB 5116405BT-60 HYB 5116405BT-70 HYB 5117405BJ-50 HYB 5117405BJ-60 HYB 5117405BJ-70 HYB 5117405BT-50 HYB 5117405BT-60 HYB 5117405BT-70 Pin Names A0-A11 A0-A9 A0-A10 RAS OE I/O1-I/O4 CAS WE Row Address Inputs for HYB5116405 Column Address Inputs for HYB5116405 Row and Column Address Inputs for HYB5117405 Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code Q67100-Q1098 Q67100-Q1099 Q67100-Q1100 on request on request on request Q67100-Q1101 Q67100-Q1102 Q67100-Q1103 on request on request on request Package P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
VCC VSS
N.C.
Semiconductor Group
2
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
P-SOJ-26/24 300 mil P-TSOPII-26/24 300 mil
Vcc I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 8 9 10 11 12 13
26 25 24 23 22 21 19 18 17 16 15 14
Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss
Vcc I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 8 9 10 11 12 13
26 25 24 23 22 21 19 18 17 16 15 14
Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss
HYB 5116405 BJ/BT
HYB 5117405 BJ/BT
Pin Configuration
Semiconductor Group
3
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
I/O1 I/O2 I/O3 I/O4
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator
Data out Buffer 4
OE
4
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
4
Refresh Counter (12) 12 Row
1024 x4
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096x1024x4
RAS
No. 1 Clock
Generator
Voltage Down Generator
VCC VCC (internal)
Block Diagram for HYB 5116405
Semiconductor Group
4
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
I/O1 I/O2 I/O3 I/O4
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator
Data out Buffer 4
OE
4
11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
Column Address Buffer(11)
11
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
4
Refresh Counter (11) 11 Row
2048 x4
Address Buffers(11)
11
Decoder 2048
Row
Memory Array 2048x2048x4
RAS
No. 1 Clock
Generator
Voltage Down Generator
VCC VCC (internal)
Block Diagram for HYB 5117405
Semiconductor Group
5
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics( note : values in brackets for HYB 5117405 BJ/BT) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %; tT = 2 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling: tRC = tRC min.) Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 10 10 2.4 - 0.5 2.4 - - 10 - 10 Unit Test Condition V V V V A A 1) 1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
- - - - - - -
100(120) mA 90 (110) mA 80 (100) mA 2 mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling, CAS = VIH, tRC = tRC min.)
-
2) 4) 2) 4) 2) 4)
ICC3
100(120) mA 90 (110) mA 80 (100) mA
Semiconductor Group
6
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
DC Characteristics( note : values in brackets for HYB 5117405 BJ/BT) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %; tT = 2 ns Parameter Symbol Limit Values min. Average VCC supply current, ICC4 during hyper page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling:tPC = tPC min.) - - - - max. 70 (70) 55 (55) 45 (45) 1 Unit Test Condition mA mA mA mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
Standby VCC supply current (RAS = CAS = VCC - 0.2 V)
Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling: tRC = tRC min.)
ICC5 ICC6
1)
- - -
100(120) mA 90 (110) mA 80 (100) mA 1 mA
2) 4) 2) 4) 2) 4)
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc - 0.2V or 0.2V)
ICC7
_
Capacitance TA = 0 to 70 C,VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10,A11) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O4) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
7
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 53 35 - - - 50 64 32 max. min. - - 10k 10k - - - - 37 25 104 40 60 10 0 10 0 10 14 12 15 50 - 50 64 32 5 1 - - max. min. - - 10k 10k - - - - 45 30 - - - 50 64 32 124 50 70 12 0 10 0 12 14 12 17 60 5 1 - -
Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for HYB5116405 Refresh period for HYB5117405 tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF 84 30 50 8 0 8 0 8 12 10 13 40 5 1 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7
Read Cycle
Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF - - - - 25 0 0 0 0 0 50 13 25 13 - - - - - 13 - - - - 30 0 0 0 0 0 60 15 30 15 - - - - - 15 - - - - 35 0 0 0 0 0 70 17 35 17 - - - - - 17 ns ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL
Semiconductor Group
8
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. -60 0 0 0 13 13 15 - - - - 0 0 0 15 15 -70 max. 17 - - - - max. min. 13 - - - - max. min.
Unit Note
Output turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tOEZ tDZC tDZO tCDD tODD
0 0 0 10 10
ns ns ns ns ns
12 13 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 8 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - 10 10 0 17 17 0 12 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time tDS tDH
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tRWC tRWD tCWD tOEH 113 64 27 39 10 - - - - - 138 77 32 47 13 - - - - - 162 89 36 54 15 - - - - - ns ns ns ns ns 15 15 15
Column address to WE delay time tAWD
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS Delay tHPC tCP tCPA tCOH tRAS tRHPC 20 8 - 5 50 27 - - 27 - - 25 10 - 5 32 - - 32 - - 30 10 - 5 37 - - 37 - - ns ns ns ns ns 7
200k 60
200k 70
200k ns
Semiconductor Group
9
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. -60 -70 max. max. min. max. min.
Unit Note
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) readwrite cycle time CAS precharge to WE tPRWC tCPWD 58 41 - - 68 49 - - 77 56 - - ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 - 40 - 40 - ns
Self Refresh Cycle
RAS pulse width RAS precharge CAS hold time tRASS tRPS tCHS 100k _ 95 -50 _ _ 100k _ 110 -50 _ _ 100k _ 130 -50 _ _ ns ns ns 17 17 17
Test Mode
Write command setup time Write command hold time CAS hold time tWTS tWTH tCHRT 10 10 30 - - - 10 10 30 - - - 10 10 30 - - - ns ns ns
Semiconductor Group
10
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA,tCPA, tOEA . tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh
Semiconductor Group
11
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column
tASR
Row
Address
V IH VIL
Row
tRCH tRAH tRCS tRRH tAA tOEA
V
WE
IH
VIL
OE
V IH VIL
tDZC tDZO tODD tCAC tCLZ
Hi Z
tCDD
I/O (Inputs)
V
IH
VIL
tOFF tOEZ
Valid Data Out Hi Z
I/O (Outputs) V
V OH OL
tRAC
"H" or "L"
WL1
Read Cycle
Semiconductor Group
12
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V IH
CAS
VIL
tRAD tASR tASC
tASR
Row
Address
V IH VIL
.
Row
tRAH
V
tWCS t WP
tCWL
WE
IH
VIL
tWCH tRWL
OE
V IH VIL
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
"H" or "L"
WL2
Write Cycle (Early Write)
Semiconductor Group
13
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
CAS
VIL
tRAD tASR tASC tCAH
Column
tASR
. Row
V
IH
Address V IL
Row
tRAH
V
WE
IH
tCWL tRWL tWP
VIL
tOEH
V
OE
IH
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tODD tDS tOEZ tCLZ tOEA
tDH
Valid Data
OH I/O (Outputs) V OL
V
Hi-Z
Hi-Z
"H" or "L"
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
14
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRWC tRAS
V IH VIL V IH
tRP
RAS
tCSH tRCD tRSH tCAS tCRP
CAS
VIL
tRAH tASR
V
tCAH tASC
Column
tASR
Row
Address
IH
VIL
Row
tRAD
V
tAWD tCWD tRWD
tCWL tRWL tWP
IH
WE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tDS tDH
Valid Data in
tCLZ tCAC
tODD tOEZ
Data Out
I/O (Outputs) V OL
V OH
tRAC
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
15
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRAS
V
tRP tRHCP tRSH tCRP
RAS
IH
tRCD
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL Column 1
tRAD tRRH tRCH
tRCS
WE
VIH VIL
tOES
V
tCAC tAA tCPA
tCAC tAA tCPA
tOFF
OE
OH OL
tOEA tRAC tAA tCAC
V
tOEZ tCOH tCOH
Data Out 2 Data Out N
I/O IH (Output) V IL
V
tCLZ
Data Out 1
"H" or "L"
WL5
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
16
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRAS
V IH
tRP tRHCP tRSH tCRP
tRCD
RAS
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row Addr
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
V
Address
IH
VIL
Column 1
tRAD tCWL tWCS
VIH VIL
tCWL tWCH tWP tWCS
tRWL tCWL tWCH tWP
tWCH tWCS tWP
WE
V
OE
OH OL
V
tDS
V IH
tDH
tDS
tDH
tDS
tDH
I/O (Input) V IL
Data In 1
Data In 2
Data In N
"H" or "L"
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
17
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Row Column
V
RAS
IH
V IL
tCSH tRCD tCAS tRAL tCRP tRSH
Semiconductor Group
V
CAS
IH
V IL
tRAD tCAH tASC
Column
tASR
tRAH
tCAH
tASR
V
Address
IH
V IL
Row
V
tRCS tAWD tOEA tOEA tWP tWP tOEA tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WE
IH
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
18
V IL
tAA
tWP
V
IH
OE
V IL
tCPA tDZC
Data In
tCPA tODD
Data In
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tDS
Data Out Data Out
tDZC tCLZ tOEH
tODD
Data In
I/O (Inputs) V IL
tODD tAA
tOEH tOEZ tDS tDH
tOEH tCAC tAA tDS
Data Out
tDH
OH I/O (Outputs) V
V
OL
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
WL17
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
CAS
V IH VIL
tRAH tASR
tASR
Row
V
Address
IH
VIL
Row
OH I/O (Outputs) V OL
V
HI-Z
"H" or "L"
WL9
RAS-Only Refresh Cycle
Semiconductor Group
19
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
CAS
V IH VIL
tWRP tWRH
V IH
WE
VIL
tOEZ
V
OE
IH
VIL
tCDD
I/O (Inputs)
V IH
VIL
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
"H" or "L"
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
20
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
CAS
IH
VIL
tRAD tASC tASR tRAH
Row
tWRP tCAH tWRH tASR
Row
V
Address
IH
VIL
Column
tRCS
V
tRRH
WE
IH
VIL
tAA tOEA
V
OE
IH
VIL
tDZC tDZO
tCDD tODD tCAC tCLZ
V
I/O (Inputs)
IH
VIL
tOFF tOEZ
Valid Data Out HI-Z
tRAC
OH I/O (Outputs) V OL V
"H" or "L"
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
21
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRC tRP
V IH
tRC tRP tRAS
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
CAS
VIL
tRAD tRAH tASR tASC tCAH
Column
tASR
Row
V
Address
IH
VIL
Row
tWCS
tWCH tWP
tWRP
tWRH
V
WE
IH
VIL
tDS
V
tDH
Valid Data
I/O (Input)
IH
V IL
OH I/O (Output) V OL
V
HI-Z
"H" or "L"
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
22
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRP
RAS
V IH VIL
tRASS
tRPS
tRPC tCSR
V
tCHS
tCRP
tCP
IH
CAS
VIL
tWRP tWRH
V
WE
IH
VIL
OE
V IH VIL
tCDD
I/O (Inputs)
V IH
VIL
tODD tOEZ
OH I/O (Outputs) V OL
V
HI-Z
tOFF
"H" or "L"
WL13
CAS before RAS Self Refresh Cycle
Semiconductor Group
23
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRAS
Read Cycle:
RAS
V IH V IL
tRP
tCSR
CAS
V IH V IL
tCHR
tCP
tRSH tCAS tRAL
tASC
Address
V IH V IL
tCAH tAA tCAC
tASR
Row
Column
tWRP
WE
V IH V IL V IH V IL V IH V IL VOH VOL
tRRH tOEA tCDD tOFF tOEZ
Data Out
tRCH
tWRH
tRCS tDZC tDZO tCLZ
OE I/O (Inputs)
tODD
I/O (Outputs)
tWRP
Write Cycle:
WE
V IH V IL
tWCS
tRWL tCWL tWCH
tWRH
OE
V IH V IL
tDS
I/O (Inputs) I/O (Outputs)
V IH V IL V IH V IL
tDH
Data In
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 24
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
tRP
V
tRC tRAS tRP
RAS
IH
VIL
tRPC tCP tCSR tCHR tRPC tCRP
V
CAS
IH
VIL
tASR tRAH
Address IH
VIL V
Row
tWTS
V
tWTH
WE
IH
VIL
V
OE
IH
VIL
I/O IH (Inputs) V IL
V
tODD
HI-Z
tCDD tOEZ
I/O (Outputs) V
V OH OL
HI-Z
tOFF
"H" or "L"
WL15
Test Mode Entry
Semiconductor Group
25
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
Test Mode As the HYB 5116(7)405BJ/BT is organized internally as 1M x 16-bits, a test mode cycle using 4:1 compression can be used to improve test time. Note that in the 4M x 4 version the test time is reduced by 1/4 for a N test pattern. In a test mode "write" the data from each I/O pin is written into four 1M blocks simultaneously (all "1" s or all "0" s). In test mode "read" each I/O output is used for indicating the test mode result. If the internal four bits are equal, the I/O would indicate a "1". If they were not equal, the I/O would indicate a "0". The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a "CAS before RAS refresh", "RAS only refresh" or "Hidden refresh" can be used.Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other addresses are don't care.
Semiconductor Group
26
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
A0C,A1C A0C,A1C Normal
1 M Block 1 M Block 1 M Block 1 M Block
Test A0C,A1C Normal
Vcc
I/O 1
Test
I/O 1
Vss Vcc
A0C,A1C Normal
1 M Block 1 M Block 1 M Block 1 M Block
A0C,A1C Normal
I/O 2
Test
I/O 2
Test
Vss Vcc
A0C,A1C Normal
1 M Block 1 M Block
Normal
I/O 3
Test
1 M Block 1 M Block
Test A0C,A1C
I/O 3
Vss Vcc
A0C,A1C Normal
1 M Block 1 M Block 1 M Block 1 M Block
Test Normal
I/O 4
Test
I/O 4
Vss
Block Diagram in Test Mode
Semiconductor Group
27
HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM
Package Outlines
GPJ05628
Plastic Package P-TSOPII-26/24 (300mil) (Thin small outline package, SMD)
7.62
+ 0.13 -
1.27
0.6
-0.2
0.4
+0.12 -0.1
26
0.2
M
24x
0.1
9.22
+ 0.2 -
14 GPX05857
1 17.27
13
-0.25
1)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
Semiconductor Group
28

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